// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VRISCV_BOARD.h for the primary calling header

#include "verilated.h"
#include "verilated_dpi.h"

#include "VRISCV_BOARD___024root.h"

VL_ATTR_COLD void VRISCV_BOARD___024root___eval_static(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval_static\n"); );
}

VL_ATTR_COLD void VRISCV_BOARD___024root___eval_initial__TOP(VRISCV_BOARD___024root* vlSelf);

VL_ATTR_COLD void VRISCV_BOARD___024root___eval_initial(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval_initial\n"); );
    // Body
    VRISCV_BOARD___024root___eval_initial__TOP(vlSelf);
    vlSelf->__Vtrigrprev__TOP__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel 
        = vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel;
    vlSelf->__Vtrigrprev__TOP__clk = vlSelf->clk;
}

VL_ATTR_COLD void VRISCV_BOARD___024root___eval_initial__TOP(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval_initial__TOP\n"); );
    // Body
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_allowin = 1U;
}

VL_ATTR_COLD void VRISCV_BOARD___024root___eval_final(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval_final\n"); );
}

VL_ATTR_COLD void VRISCV_BOARD___024root___eval_triggers__stl(VRISCV_BOARD___024root* vlSelf);
#ifdef VL_DEBUG
VL_ATTR_COLD void VRISCV_BOARD___024root___dump_triggers__stl(VRISCV_BOARD___024root* vlSelf);
#endif  // VL_DEBUG
VL_ATTR_COLD void VRISCV_BOARD___024root___eval_stl(VRISCV_BOARD___024root* vlSelf);

VL_ATTR_COLD void VRISCV_BOARD___024root___eval_settle(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval_settle\n"); );
    // Init
    CData/*0:0*/ __VstlContinue;
    // Body
    vlSelf->__VstlIterCount = 0U;
    __VstlContinue = 1U;
    while (__VstlContinue) {
        __VstlContinue = 0U;
        VRISCV_BOARD___024root___eval_triggers__stl(vlSelf);
        if (vlSelf->__VstlTriggered.any()) {
            __VstlContinue = 1U;
            if (VL_UNLIKELY((0x64U < vlSelf->__VstlIterCount))) {
#ifdef VL_DEBUG
                VRISCV_BOARD___024root___dump_triggers__stl(vlSelf);
#endif
                VL_FATAL_MT("/home/finalx/ysyx-workbench/npc/vsrc/RISCV_BOARD.v", 3, "", "Settle region did not converge.");
            }
            vlSelf->__VstlIterCount = ((IData)(1U) 
                                       + vlSelf->__VstlIterCount);
            VRISCV_BOARD___024root___eval_stl(vlSelf);
        }
    }
}

#ifdef VL_DEBUG
VL_ATTR_COLD void VRISCV_BOARD___024root___dump_triggers__stl(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___dump_triggers__stl\n"); );
    // Body
    if ((1U & (~ (IData)(vlSelf->__VstlTriggered.any())))) {
        VL_DBG_MSGF("         No triggers active\n");
    }
    if (vlSelf->__VstlTriggered.at(0U)) {
        VL_DBG_MSGF("         'stl' region trigger index 0 is active: Internal 'stl' trigger - first iteration\n");
    }
    if (vlSelf->__VstlTriggered.at(1U)) {
        VL_DBG_MSGF("         'stl' region trigger index 1 is active: @([hybrid] RISCV_BOARD.cpu.id_stage.imm_sel)\n");
    }
}
#endif  // VL_DEBUG

VL_ATTR_COLD void VRISCV_BOARD___024root___stl_sequent__TOP__0(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___stl_sequent__TOP__0\n"); );
    // Init
    VlWide<7>/*223:0*/ __Vtemp_h10a86387__0;
    // Body
    vlSelf->debug_wb_pc = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[3U] 
                            << 0x1eU) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[2U] 
                                         >> 2U));
    if ((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])) {
        vlSelf->RISCV_BOARD__DOT__data_sram_wmask = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rdbypass = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rdbypass = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h255a08e4__0 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[0U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[1U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[2U] = 0U;
    } else {
        vlSelf->RISCV_BOARD__DOT__data_sram_wmask = 
            (0xfU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                     >> 0x14U));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rdbypass 
            = (0x1fU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                        >> 0xfU));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rdbypass 
            = (0x1fU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[3U] 
                        >> 2U));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h255a08e4__0 
            = (0x1fU & ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[8U] 
                         << 4U) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                                   >> 0x1cU)));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 
            = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[9U] 
                << 4U) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[8U] 
                          >> 0x1cU));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2 
            = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[8U] 
                << 4U) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                          >> 0x1cU));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[0U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[0U];
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[1U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[1U];
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[2U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[2U];
    }
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_store 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                    >> 0x1bU)));
    vlSelf->debug_wb_rf_waddr = (0x1fU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[4U] 
                                          >> 2U));
    vlSelf->debug_wb_rf_wdata = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[4U] 
                                  << 0x1eU) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[3U] 
                                               >> 2U));
    vlSelf->debug_wb_rf_wen = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[6U] 
                                >> 0x14U) & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__wb_valid));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rfwenbypass 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[6U] 
                    >> 0x18U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT____VdfgTmp_h0c27a012__0 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U] 
                    >> 0x16U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_load 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                    >> 0x1aU)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h25d289c6__0 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[8U] 
                    >> 0x1bU)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h9dbf4c0d__0 
        = (IData)(((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[9U] 
                    >> 0x1bU) & (~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sra 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                    >> 0xdU)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sub 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                    >> 5U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_slt 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                    >> 6U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sltu 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                    >> 7U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_bypass 
        = ((IData)(((vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[6U] 
                     >> 0x19U) & (~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])))
            ? ((1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                      & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U] 
                         >> 0x15U))) ? vlSelf->RISCV_BOARD__DOT__data_sram_rdata
                : ((1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                          & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U] 
                             >> 0x14U))) ? (((- (IData)(
                                                        ((vlSelf->RISCV_BOARD__DOT__data_sram_rdata 
                                                          >> 0xfU) 
                                                         & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT____VdfgTmp_h0c27a012__0)))) 
                                             << 0x10U) 
                                            | (0xffffU 
                                               & vlSelf->RISCV_BOARD__DOT__data_sram_rdata))
                    : ((1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                              & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U] 
                                 >> 0x13U))) ? (((- (IData)(
                                                            ((vlSelf->RISCV_BOARD__DOT__data_sram_rdata 
                                                              >> 7U) 
                                                             & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT____VdfgTmp_h0c27a012__0)))) 
                                                 << 8U) 
                                                | (0xffU 
                                                   & vlSelf->RISCV_BOARD__DOT__data_sram_rdata))
                        : 0U))) : ((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                    ? 0U : ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U] 
                                             << 0xdU) 
                                            | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[4U] 
                                               >> 0x13U))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_if_loadbypass 
        = ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_load) 
           & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_valid));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rfwenbypass 
        = (1U & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_load)) 
                 & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                    & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                       >> 0x19U))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_cin 
        = ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sub) 
           | ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_slt) 
              | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sltu)));
    __Vtemp_h10a86387__0[5U] = (((IData)(((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                           ? 0ULL : 
                                          (0x3ffffffffULL 
                                           & (((QData)((IData)(
                                                               vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[6U])) 
                                               << 9U) 
                                              | ((QData)((IData)(
                                                                 vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U])) 
                                                 >> 0x17U))))) 
                                 << 0x13U) | (((IData)(
                                                       ((1U 
                                                         & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                                         ? 0ULL
                                                         : 
                                                        (0x1ffffffffffffULL 
                                                         & (((QData)((IData)(
                                                                             vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[4U])) 
                                                             << 0x1eU) 
                                                            | ((QData)((IData)(
                                                                               vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[3U])) 
                                                               >> 2U))))) 
                                               >> 0x1eU) 
                                              | ((IData)(
                                                         (((1U 
                                                            & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                                            ? 0ULL
                                                            : 
                                                           (0x1ffffffffffffULL 
                                                            & (((QData)((IData)(
                                                                                vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[4U])) 
                                                                << 0x1eU) 
                                                               | ((QData)((IData)(
                                                                                vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[3U])) 
                                                                  >> 2U)))) 
                                                          >> 0x20U)) 
                                                 << 2U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[3U] 
        = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_bypass 
            << 2U) | ((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                       ? 0U : (3U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[3U])));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[4U] 
        = (((IData)(((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                      ? 0ULL : (0x1ffffffffffffULL 
                                & (((QData)((IData)(
                                                    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[4U])) 
                                    << 0x1eU) | ((QData)((IData)(
                                                                 vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[3U])) 
                                                 >> 2U))))) 
            << 2U) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_bypass 
                      >> 0x1eU));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[5U] 
        = __Vtemp_h10a86387__0[5U];
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[6U] 
        = (((IData)(((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                      ? 0ULL : (0x3ffffffffULL & (((QData)((IData)(
                                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[6U])) 
                                                   << 9U) 
                                                  | ((QData)((IData)(
                                                                     vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U])) 
                                                     >> 0x17U))))) 
            >> 0xdU) | ((IData)((((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                   ? 0ULL : (0x3ffffffffULL 
                                             & (((QData)((IData)(
                                                                 vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[6U])) 
                                                 << 9U) 
                                                | ((QData)((IData)(
                                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U])) 
                                                   >> 0x17U)))) 
                                 >> 0x20U)) << 0x13U));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_to_id_valid 
        = ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_if_loadbypass)) 
           & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_valid));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_to_exe_valid 
        = ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_if_loadbypass)) 
           & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_valid));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_allowin 
        = (1U & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_valid)) 
                 | ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_if_loadbypass)) 
                    & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_allowin))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_b 
        = ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_cin)
            ? ((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                ? 0xffffffffU : (~ ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[8U] 
                                     << 4U) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                                               >> 0x1cU))))
            : vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_allowin 
        = (1U & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_valid)) 
                 | ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_if_loadbypass)) 
                    & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_allowin))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_result 
        = (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 
           + (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_b 
              + (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_cin)));
    vlSelf->RISCV_BOARD__DOT__inst_sram_en = ((~ (IData)(vlSelf->reset)) 
                                              & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_allowin));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result 
        = (((- (IData)((1U & (((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                               & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                  >> 4U)) | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sub))))) 
            & vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_result) 
           | ((1U & ((- (IData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_slt))) 
                     & (((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h25d289c6__0)) 
                         & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h9dbf4c0d__0)) 
                        | ((~ ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h9dbf4c0d__0) 
                               ^ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h25d289c6__0))) 
                           & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_result 
                              >> 0x1fU))))) | ((1U 
                                                & ((- (IData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sltu))) 
                                                   & (~ (IData)(
                                                                (1ULL 
                                                                 & (((QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1)) 
                                                                     + 
                                                                     ((QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_b)) 
                                                                      + (QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_cin)))) 
                                                                    >> 0x20U)))))) 
                                               | (((- (IData)(
                                                              (1U 
                                                               & ((~ 
                                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                                                  & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                     >> 8U))))) 
                                                   & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 
                                                      & vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2)) 
                                                  | (((- (IData)(
                                                                 (1U 
                                                                  & ((~ 
                                                                      vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                                                     & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                        >> 9U))))) 
                                                      & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 
                                                         | vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2)) 
                                                     | (((- (IData)(
                                                                    (1U 
                                                                     & ((~ 
                                                                         vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                                                        & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                           >> 0xaU))))) 
                                                         & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 
                                                            ^ vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2)) 
                                                        | (((- (IData)(
                                                                       (1U 
                                                                        & ((~ 
                                                                            vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                                                           & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                              >> 0xeU))))) 
                                                            & vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2) 
                                                           | (((- (IData)(
                                                                          (1U 
                                                                           & ((~ 
                                                                               vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                                                              & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                                >> 0xbU))))) 
                                                               & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 
                                                                  << (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h255a08e4__0))) 
                                                              | ((- (IData)(
                                                                            (1U 
                                                                             & (((~ 
                                                                                vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                                                                & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                                >> 0xcU)) 
                                                                                | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sra))))) 
                                                                 & (IData)(
                                                                           ((((QData)((IData)(
                                                                                (- (IData)(
                                                                                ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sra) 
                                                                                & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h9dbf4c0d__0)))))) 
                                                                              << 0x20U) 
                                                                             | (QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1))) 
                                                                            >> (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h255a08e4__0))))))))))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass 
        = (1U & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U] 
                 | ((((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result) 
                      & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                         & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[4U] 
                            >> 3U))) | ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                        & ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[4U] 
                                            >> 2U) 
                                           & vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result))) 
                    & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_valid))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_identIMM__DOT____VdfgTmp_h78278846__0 
        = ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)) 
           & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
              >> 0x1fU));
    if (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass) {
        vlSelf->__VdfgTmp_hea37eb48__0 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__func3 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op = 0U;
    } else {
        vlSelf->__VdfgTmp_hea37eb48__0 = (0x1fU & (
                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                                                   >> 7U));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2 
            = (0x1fU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                        >> 0x14U));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1 
            = (0x1fU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                        >> 0xfU));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__func3 
            = (7U & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                     >> 0xcU));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op 
            = (0x1fU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                        >> 2U));
    }
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op_ebreak 
        = (1U & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                    >> 0x14U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2 
        = (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rfwenbypass) 
            & (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rdbypass) 
                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2)) 
               & (0U != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2))))
            ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result
            : (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rfwenbypass) 
                & (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rdbypass) 
                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2)) 
                   & (0U != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2))))
                ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_bypass
                : (((IData)(vlSelf->debug_wb_rf_wen) 
                    & (((IData)(vlSelf->debug_wb_rf_waddr) 
                        == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2)) 
                       & (0U != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2))))
                    ? vlSelf->debug_wb_rf_wdata : (
                                                   (0U 
                                                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2))
                                                    ? 0U
                                                    : 
                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf
                                                   [vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2]))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1 
        = (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rfwenbypass) 
            & (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rdbypass) 
                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1)) 
               & (0U != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1))))
            ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result
            : (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rfwenbypass) 
                & (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rdbypass) 
                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1)) 
                   & (0U != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1))))
                ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_bypass
                : (((IData)(vlSelf->debug_wb_rf_wen) 
                    & (((IData)(vlSelf->debug_wb_rf_waddr) 
                        == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1)) 
                       & (0U != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1))))
                    ? vlSelf->debug_wb_rf_wdata : (
                                                   (0U 
                                                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1))
                                                    ? 0U
                                                    : 
                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf
                                                   [vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1]))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37 
        = (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op) 
            << 4U) | (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__func3) 
                       << 1U) | (1U & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)) 
                                       & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                                          >> 0x1eU)))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3 
        = (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op) 
            << 3U) | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__func3));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__branch_rs1_eq_rs2 
        = (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1 
           == vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_ecall 
        = ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op_ebreak)) 
           & (0x1c0U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__dst_store 
        = ((0x40U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
           | ((0x41U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
              | (0x42U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_4 
        = ((0x1bU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)) 
           | (0xc8U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_branch_blt 
        = ((0xc4U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
           | (0xc6U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__inst_lb 
        = ((0U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
           & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)) 
              & vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U]));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____VdfgTmp_h141f93ed__0 
        = ((((0xc0U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
             & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__branch_rs1_eq_rs2)) 
            | ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__branch_rs1_eq_rs2)) 
               & (0xc1U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)))) 
           | (0x1bU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_rs2 
        = ((0xc0U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
           | ((0xc1U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
              | ((0xc2U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                 | ((0xc4U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                    | ((0xc6U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                       | ((0xc8U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                          | ((0xcaU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                             | ((0xcbU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                | ((0xccU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                   | ((0xceU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                      | ((0xc5U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                         | ((0xc7U 
                                             == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                            | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_branch_blt)))))))))))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__alu_op 
        = ((((0xdU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)) 
             | (0xe1U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
            << 0xaU) | ((((0xcbU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                          | (0x4bU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37))) 
                         << 9U) | ((((0xcaU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                     | (0x4aU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37))) 
                                    << 8U) | ((((0xc2U 
                                                 == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                | (0x42U 
                                                   == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37))) 
                                               << 7U) 
                                              | ((((0xc8U 
                                                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                   | (0x24U 
                                                      == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                                  << 6U) 
                                                 | ((((0xccU 
                                                       == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                      | (0x26U 
                                                         == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                                     << 5U) 
                                                    | ((((0xceU 
                                                          == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                         | (0x27U 
                                                            == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                                        << 4U) 
                                                       | ((((0xc6U 
                                                             == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                            | ((0x23U 
                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                               | ((0xc7U 
                                                                   == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                  | (0xc6U 
                                                                     == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))))) 
                                                           << 3U) 
                                                          | ((((0xc4U 
                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                               | ((0x22U 
                                                                   == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                  | ((0xc5U 
                                                                      == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                     | (0xc4U 
                                                                        == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))))) 
                                                              << 2U) 
                                                             | (((0xc1U 
                                                                  == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                                 << 1U) 
                                                                | ((0xc0U 
                                                                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                                   | ((0x20U 
                                                                       == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                      | ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__inst_lb) 
                                                                         | ((4U 
                                                                             == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                            | ((1U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                               | ((5U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                                | ((2U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                                | ((0x40U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                                | ((0x41U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                                | ((0x42U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                                | ((0x1bU 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)) 
                                                                                | ((0xc8U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                                | (5U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op))))))))))))))))))))))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_to_if_brjmpbypass 
        = ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass) 
           | (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____VdfgTmp_h141f93ed__0) 
               | (0xc8U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
              & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_valid)));
}

void VRISCV_BOARD___024root___act_sequent__TOP__0(VRISCV_BOARD___024root* vlSelf);

VL_ATTR_COLD void VRISCV_BOARD___024root___eval_stl(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval_stl\n"); );
    // Body
    if (vlSelf->__VstlTriggered.at(0U)) {
        VRISCV_BOARD___024root___stl_sequent__TOP__0(vlSelf);
    }
    if ((vlSelf->__VstlTriggered.at(0U) | vlSelf->__VstlTriggered.at(1U))) {
        VRISCV_BOARD___024root___act_sequent__TOP__0(vlSelf);
    }
}

#ifdef VL_DEBUG
VL_ATTR_COLD void VRISCV_BOARD___024root___dump_triggers__ico(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___dump_triggers__ico\n"); );
    // Body
    if ((1U & (~ (IData)(vlSelf->__VicoTriggered.any())))) {
        VL_DBG_MSGF("         No triggers active\n");
    }
    if (vlSelf->__VicoTriggered.at(0U)) {
        VL_DBG_MSGF("         'ico' region trigger index 0 is active: Internal 'ico' trigger - first iteration\n");
    }
}
#endif  // VL_DEBUG

#ifdef VL_DEBUG
VL_ATTR_COLD void VRISCV_BOARD___024root___dump_triggers__act(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___dump_triggers__act\n"); );
    // Body
    if ((1U & (~ (IData)(vlSelf->__VactTriggered.any())))) {
        VL_DBG_MSGF("         No triggers active\n");
    }
    if (vlSelf->__VactTriggered.at(0U)) {
        VL_DBG_MSGF("         'act' region trigger index 0 is active: @([hybrid] RISCV_BOARD.cpu.id_stage.imm_sel)\n");
    }
    if (vlSelf->__VactTriggered.at(1U)) {
        VL_DBG_MSGF("         'act' region trigger index 1 is active: @(posedge clk)\n");
    }
}
#endif  // VL_DEBUG

#ifdef VL_DEBUG
VL_ATTR_COLD void VRISCV_BOARD___024root___dump_triggers__nba(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___dump_triggers__nba\n"); );
    // Body
    if ((1U & (~ (IData)(vlSelf->__VnbaTriggered.any())))) {
        VL_DBG_MSGF("         No triggers active\n");
    }
    if (vlSelf->__VnbaTriggered.at(0U)) {
        VL_DBG_MSGF("         'nba' region trigger index 0 is active: @([hybrid] RISCV_BOARD.cpu.id_stage.imm_sel)\n");
    }
    if (vlSelf->__VnbaTriggered.at(1U)) {
        VL_DBG_MSGF("         'nba' region trigger index 1 is active: @(posedge clk)\n");
    }
}
#endif  // VL_DEBUG

VL_ATTR_COLD void VRISCV_BOARD___024root___ctor_var_reset(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___ctor_var_reset\n"); );
    // Body
    vlSelf->clk = VL_RAND_RESET_I(1);
    vlSelf->reset = VL_RAND_RESET_I(1);
    vlSelf->debug_wb_pc = VL_RAND_RESET_I(32);
    vlSelf->debug_wb_rf_wen = VL_RAND_RESET_I(1);
    vlSelf->debug_wb_rf_waddr = VL_RAND_RESET_I(5);
    vlSelf->debug_wb_rf_wdata = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__inst_sram_en = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__inst_sram_addr = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__inst_sram_rdata = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__data_sram_rdata = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__data_sram_wmask = VL_RAND_RESET_I(4);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_allowin = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_allowin = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_to_id_valid = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_to_exe_valid = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(213, vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rdbypass = VL_RAND_RESET_I(5);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rfwenbypass = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_bypass = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rdbypass = VL_RAND_RESET_I(5);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rfwenbypass = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_if_loadbypass = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_to_if_brjmpbypass = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_pc = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_valid = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_allowin = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_valid = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(96, vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op = VL_RAND_RESET_I(5);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1 = VL_RAND_RESET_I(5);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2 = VL_RAND_RESET_I(5);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__func3 = VL_RAND_RESET_I(3);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel = VL_RAND_RESET_I(5);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__alu_op = VL_RAND_RESET_I(11);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__branch_rs1_eq_rs2 = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_branch_blt = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_ecall = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op_ebreak = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37 = VL_RAND_RESET_I(9);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3 = VL_RAND_RESET_I(8);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1 = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2 = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____VdfgTmp_h141f93ed__0 = 0;
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_rs2 = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_4 = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__dst_store = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__inst_lb = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_identIMM__DOT____VdfgTmp_h78278846__0 = 0;
    for (int __Vi0 = 0; __Vi0 < 32; ++__Vi0) {
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf[__Vi0] = VL_RAND_RESET_I(32);
    }
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_cf__DOT__mtvec = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_valid = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(316, vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2 = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_load = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_store = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sub = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_slt = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sltu = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sra = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_b = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_cin = VL_RAND_RESET_I(1);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_result = VL_RAND_RESET_I(32);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h25d289c6__0 = 0;
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h9dbf4c0d__0 = 0;
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h255a08e4__0 = 0;
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__mem_valid = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(218, vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT____VdfgTmp_h0c27a012__0 = 0;
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__wb_valid = VL_RAND_RESET_I(1);
    VL_RAND_RESET_W(213, vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r);
    vlSelf->__VdfgTmp_hea37eb48__0 = 0;
    vlSelf->__Vtrigrprev__TOP__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel = VL_RAND_RESET_I(5);
    vlSelf->__VstlDidInit = 0;
    vlSelf->__Vtrigrprev__TOP__clk = VL_RAND_RESET_I(1);
    vlSelf->__VactDidInit = 0;
}
